This thesis delves into the creation and application of a predictive model aimed at optimizing chip production on a wafer, while maintaining the on-resistance (Ron) of a MOSFET within acceptable limits. Through a systematic approach, various regression models were developed, including linear regression, Random Forest, XGBoost, and a Deep Neural Network (DNN), to predict chip quantities considering both wafer and chip geometry. Model performance was rigorously evaluated using mean absolute error, with a focus on comparing machine learning models to a geometry-based predictor. The DNN demonstrated superior accuracy and was integrated into an optimization algorithm that managed the balance between chip quantity and Ron value. This algorithm employed Differential Evolution to identify the optimal chip layout, expanding its scope by considering reticle-based scenarios. This work contributes valuable insights into semiconductor manufacturing and chip layout optimization, offering a method to enhance wafer productivity, efficiency, and cost-effectiveness.
Anotace v angličtině
This thesis delves into the creation and application of a predictive model aimed at optimizing chip production on a wafer, while maintaining the on-resistance (Ron) of a MOSFET within acceptable limits. Through a systematic approach, various regression models were developed, including linear regression, Random Forest, XGBoost, and a Deep Neural Network (DNN), to predict chip quantities considering both wafer and chip geometry. Model performance was rigorously evaluated using mean absolute error, with a focus on comparing machine learning models to a geometry-based predictor. The DNN demonstrated superior accuracy and was integrated into an optimization algorithm that managed the balance between chip quantity and Ron value. This algorithm employed Differential Evolution to identify the optimal chip layout, expanding its scope by considering reticle-based scenarios. This work contributes valuable insights into semiconductor manufacturing and chip layout optimization, offering a method to enhance wafer productivity, efficiency, and cost-effectiveness.
This thesis delves into the creation and application of a predictive model aimed at optimizing chip production on a wafer, while maintaining the on-resistance (Ron) of a MOSFET within acceptable limits. Through a systematic approach, various regression models were developed, including linear regression, Random Forest, XGBoost, and a Deep Neural Network (DNN), to predict chip quantities considering both wafer and chip geometry. Model performance was rigorously evaluated using mean absolute error, with a focus on comparing machine learning models to a geometry-based predictor. The DNN demonstrated superior accuracy and was integrated into an optimization algorithm that managed the balance between chip quantity and Ron value. This algorithm employed Differential Evolution to identify the optimal chip layout, expanding its scope by considering reticle-based scenarios. This work contributes valuable insights into semiconductor manufacturing and chip layout optimization, offering a method to enhance wafer productivity, efficiency, and cost-effectiveness.
Anotace v angličtině
This thesis delves into the creation and application of a predictive model aimed at optimizing chip production on a wafer, while maintaining the on-resistance (Ron) of a MOSFET within acceptable limits. Through a systematic approach, various regression models were developed, including linear regression, Random Forest, XGBoost, and a Deep Neural Network (DNN), to predict chip quantities considering both wafer and chip geometry. Model performance was rigorously evaluated using mean absolute error, with a focus on comparing machine learning models to a geometry-based predictor. The DNN demonstrated superior accuracy and was integrated into an optimization algorithm that managed the balance between chip quantity and Ron value. This algorithm employed Differential Evolution to identify the optimal chip layout, expanding its scope by considering reticle-based scenarios. This work contributes valuable insights into semiconductor manufacturing and chip layout optimization, offering a method to enhance wafer productivity, efficiency, and cost-effectiveness.
The student presented his work within the given time (5 minutes faster than expected). He was pretty hard to understand as his presentation pace was very fast.
The second opponent is proposing a grade between A and B.
What are the features of the correlation matrix?
Could you show the slide with the testing and validation? Could you address the size of the dataset? Did you have enough data to train the network?
What were the absolute errors?
Are the data for the testing and training available somewhere?